(a) Field of the Invention
The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption.
(b) Background Art
For a typical memory, an address in which a data is stored must be correctly confirmed in order to allow access to the stored data. However, a content addressable memory (CAM) is a memory having a function in which although a correct address in which a data is stored is not confirmed, when the content of the data is entered, an address of a location where the data of an associated content is stored can be found out. Thus, in the case where a specific content is searched from a number of data, owing to a unique fast search characteristic in which a data associated with a data matching a given content can be found out, IP address lookup methods using the content addressable memory (CAM) are widely used and are also utilized variously in a data search engine.
Such a content addressable memory can be largely divided into a binary content addressable memory (BCAM) and a ternary content addressable memory (TCAM). The binary content addressable memory (BCMA) is configured such that a data “0” or “1” is stored in a memory cell, and an input data and a stored data are compared with each other to search for an address of a location where the data of an associated content is stored. On the contrary, the ternary content addressable memory (TCAM) is configured such that a data “don't care” can be stored besides the data “0” or “1”, and such that even in the case where the stored data is searched, a combination of “0”, “1” and “don't care” is inputted and an input data and a stored value are compared with each other to search for an address of a location where the data of an associated content is stored.
FIG. 1 is a schematic diagram showing one example of searching for data stored in a binary content addressable memory (BCAM), wherein FIG. 1(a) shows data which it is desired to search, and FIG. 1(b) shows data stored in the binary content addressable memory (BCAM). As shown in FIG. 1(a), the data which it is desired to search includes 1, 1, 0, 1, 0, 0 and 1. The binary content addressable memory compares an input data and a stored data, and searches, as a matching data, the data which matches the input data among the data stored in the binary content addressable memory (BCAM), i.e., the data stored in a third row of the stored data as shown in FIG. 2(b). In this manner, since the binary content addressable memory searches the data of a content which matches an input data in its entirety from the data stored therein., although an address in which an associated input data is stored is not confirmed, a matching data of the associated input data can be searched from the stored data only by using the content of the associated input data
FIG. 2 is a schematic circuit diagram showing a conventional binary content addressable memory (BCAM).
Referring to FIG. 2, the conventional binary content addressable memory includes: a storage unit 10 for storing data of “0” and “1”; a bit line portion for inputting a data to be stored in the storage unit 10 or inputting a comparison data used to determine the stored data, the bit line portion being composed of a first bit line BL and a second bit line BL/; a word line WL for controlling the activation of the storage unit 10; and a comparator circuit unit 20 for comparing the comparison data inputted through the bit line portion BL and BL/ with a storage data stored in the storage unit 10, and determining whether or not the storage data stored in the content addressable memory and the inputted comparison data match each other.
The storage unit 10 includes a first NMOS transistor M1 and a second NMOS transistor M2 whose sources are connected to the bit line portion BL and BL/, and a pair of inverters I1 and I2 connected with each other in a feedback loop fashion for storing the data inputted through the bit line portion BL and BL/. Each of a first inverter I1 and a second inverter I2 is composed of a PMOS transistor and a NMOS transistor.
In the meantime, the comparator circuit unit 20 includes a matching line ML precharged to a high (H) level in response to a precharge signal, a third NMOS transistor M3 and a fourth NMOS transistor M4 whose gates are connected to the pair of inverters I1 and I2 so as to be activated/deactivated by the data stored in the pair of inverters I1 and I2, and a fifth NMOS transistor M5 whose drain is connected to the matching line ML.
A drain of the third NMOS transistor M3 and a source of the fourth NMOS transistor M4 are connected to each other, and a gate of the fifth NMOS transistor M5 is connected to a node A to which the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected. In this case, a source of the fifth NMOS transistor M5 is grounded. When the data stored in the storage unit 10 is determined, the word line WL is deactivated. If it is determined that there is a mach between the comparison data inputted through the bit line portion BL and BL/ and the storage data stored in the storage unit 10, the matching line ML is maintained in a precharged state to output a high level value as a result of the comparison. On the other hand, if it is determined that there is a mismatch between the comparison data inputted through the bit line portion BL and BL/ and the storage data stored in the storage unit 10, the matching line ML is discharged to output a low level value as a result of the comparison.
As discussed above, in the conventional binary content addressable memory, data must be separately inputted to the first input line BL and the second input line BL/ in order to store the data in the storage unit 10. Furthermore, the storage unit 10 includes a plurality of transistors, i.e., a total of six (6) transistors, of which two (2) NMOS transistors M1 and M2 are connected to the input line portion BL and BL/, and four (4) transistors (not shown) constitute the pair of inverters I1 and I2. Thus, the conventional binary content addressable memory includes a total of nine (9) transistors, of which six (6) transistors are used in the storage unit 10 and three (3) transistors are used in the comparator circuit unit 20.
The most important factor which must be considered in the memory design is that the size of a memory is reduced to increase the degree of integration, and that power consumption is reduced through the high-performance design. The conventional binary content addressable memory, however, basically employs a total of nine (9) transistors, including the comparator circuit unit 20, and requires that data should be separately inputted to the first input line BL and the second input line BL/ in order to store the data in the storage unit 10.
Therefore, such a conventional binary content addressable memory has a limitation in integration and entails a problem in that a number of transistors and the first and second input lines are employed to increase power consumption and high performance is not exhibited due to complexity of the process.
The information disclosed in this background of the invention section is only for enhancement of understanding of the background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.